Is ITC Bored with Board Test?

If you look at the mix of papers published at ITC over the last ten years or so, there does appear to be a large swing away from board test topics and towards more IC-oriented technical papers. Why is that? Could one argue that board test became a solved problem after the introduction of the IEEE 1149.1 standard [1]? Hardly, since that original standard, as useful as it has proven to be, was still deficient in a number of areas and is being actively extended even today. The most notable recent extensions are the 1149.4 analog interface and the proposed P1149.6 extension for high speed digital signals. As an ASIC vendor, we work with many different companies on implementing ASICs in a variety of applications. Often, given the choice, our customers would opt not to implement boundary scan on their designs. It’s not clear if this is indicative of the perceived difficulty in using the approach, a lack of familiarity with the tools involved, the use of other more desirable solutions, or some combination of the above. Clearly, boards are not going untested. So, either via JTAG or other means, solutions exist for board level testing. But, if board manufacturers are opting for non-1149.1 test procedures, the question remains, why do we not see more active research in this area? There are probably at least two reasons: